화학공학소재연구정보센터
Journal of the Electrochemical Society, Vol.152, No.1, G107-G109, 2005
Characterization of three-dimensional capacitor prepared by oxide recess in shallow trench isolation
In this paper, we present a new process flow to increase cell capacitance in planar dynamic random access memory cells designed for system-on-chip applications. Silicon dioxide of shallow trench isolation (STI) under capacitor electrodes is recessed to increase cell capacitance. It appears that the cell capacitance is increased to 25% when the STI recess is 0.15 mum. The recession slightly decreases junction leakage current due to annealing of defects and also relief of STI stress. These combined effects increase refresh time about 50% in 1 Mb memory array. The distribution of breakdown voltage in capacitor oxide shows similar behavior compared with samples without STI recessed. Also, the lifetime of the capacitor oxide evaluated from the Weibull method exceeds 2000 years. (C) 2004 The Electrochemical Society.