Solid-State Electronics, Vol.143, 77-82, 2018
Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics
Three-dimensional (3D) Si surface nanostructuring is interesting towards increasing the capacitance density of a metal-oxidesemiconductor (MOS) capacitor, while keeping reduced footprint for miniaturization. Si nanowires (SiNWs) can be used in this respect. With the aim of understanding the electrical versus geometrical characteristics of such capacitors, we fabricated and studied a MOS capacitor with highly ordered arrays of vertical Si nanowires of different lengths and thermal silicon oxide dielectric, in comparison to similar flat MOS capacitors. The high homogeneity and ordering of the SiNWs allowed the determination of the single SiNW capacitance and intrinsic series resistance, as well as other electrical characteristics (density of interface states, flat-band voltage and leakage current) in relation to the geometrical characteristics of the SiNWs. The SiNW capacitors demonstrated increased capacitance density compared to the flat case, while maintaining a cutoff frequency above 1 MHz, much higher than in other reports in the literature. Finally, our model system has been shown to constitute an excellent platform for the study of SiNW capacitors with either grown or deposited dielectrics, as for example high-k dielectrics for further increasing the capacitance density. This will be the subject of future work.