Elsevier

Solid-State Electronics

Volume 48, Issue 8, August 2004, Pages 1417-1422
Solid-State Electronics

Investigation of strained Si/SiGe devices by MC simulation

https://doi.org/10.1016/j.sse.2004.02.016Get rights and content

Abstract

Transport in Si NMOSFETs with gate lengths from 48 to 23 nm is investigated by full-band Monte Carlo device simulation for three sets of devices: (I) unstrained Si control devices, (II) process matched strained Si devices, and (III) threshold voltage matched strained Si devices. While the process matched strained Si devices show the same performance improvement for all gate lengths, this is not the case for the threshold voltage matched devices for which the performance improvement degrades with shrinking gate length due to the heavier doping.

Introduction

The SiGe technique has made bandgap engineering and mobility enhancement by strain available in the mainstream Si technology at a more competitive cost than in III–V technologies [1], [2]. Since the on-current of a MOSFET is strongly influenced by the effective low-field mobility in the inversion layer, strained Si layers with their higher mobility can be used to improve CMOS performance [3], [4]. Strained Si will be used in future CMOS generations [5], [6], where the strain can be induced not only by a relaxed SiGe layer in the bulk but also by gate processing [7]. In order to understand the transport properties and to explore the potential of this material, microscopic simulation models have been developed (e.g. [8], [9], [10]). The Monte Carlo (MC) model is especially well suited for this material system, because it contains only a few empirical parameters in contrast to less physics-based models (i.e. drift diffusion or hydrodynamic models), which require much more calibration. Consequently, due to the large degree of freedom in the SiGe alloy configuration (strain, Ge content, effects from new materials, etc) many more measurements are required for the calibration of the classical device models than for unstrained Si, and such measurements are still largely unavailable. Therefore, microscopic models like the MC model are preferable, although they are more CPU intensive. In addition, the momentum-based models become increasingly inaccurate under quasiballistic transport conditions and their results are unreliable in sub-50 nm devices [11].

It has been experimentally observed that the performance improvement due to strain decreases at smaller gate lengths [12]. In this paper we want to quantify the performance deterioration and explain the reasons for it.

The strain in the channel region of the MOSFET not only changes the mobility but also the threshold voltage, which decreases with strain [13], [14]. Therefore, in order to properly analyze the problem, we investigated three sets of devices: Unstrained Si control devices (CD), process matched (PM) strained Si NMOSFETs, which have same doping profiles as the control devices, and threshold voltage matched (VM) strained Si devices, where the doping profile is adjusted to match the threshold voltage of the control devices. The PM case allows to investigate the impact of strain on transport under almost the same electrical conditions as in the control devices, whereas the VM case is the more realistic one, which accounts for the degradation of the mobility due to the higher doping concentration required [15], [12].

Section snippets

Simulation model

The simulation model is based on the semi-classical Boltzmann equation neglecting degeneracy [16], where the band structure of strained Si is calculated with the nonlocal empirical pseudopotential method [17]. The details of the band structure are captured completely only by the full-band MC model, which is used here [18]. The corresponding scattering algorithms are so fast, that the full-band MC model is as efficient as an analytical-band simulator, where phonon, alloy, impurity, and surface

Strained Si NMOSFETs

In Fig. 1 the drift velocity in 〈1 1 0〉 direction is shown for different strain levels in an undoped bulk system consisting solely of strained Si. The low-field mobility is enhanced by strain, whereas the saturation velocity remains unaffected [23]. In addition, the low-field mobility enhancement saturates for high strain levels. Since the performance of a MOSFET is determined by the transport in the channel, MC simulations of inversion layers, which are homogeneous parallel to the Si/SiO2

Device simulation results

The three sets of devices described above have been simulated for a gate overdrive of 0.9 V, a lattice temperature of 300 K, and the 〈1 1 0〉 channel direction. Self-heating effects have not been considered. The relaxed SiGe layer in the bulk is neglected and the whole bulk is assumed to be strained Si to allow for an easier comparison between the strained and unstrained case. Simulations including the SiGe layer showed only negligible differences in the device performance.

In Fig. 5, Fig. 6 the

Conclusions

For the same doping profiles strained Si NMOSFETs yield a considerable on-current improvement even at a gate length of 23 nm. If the doping profile is modified to match the threshold voltage of the unstrained Si devices, the performance improvement degrades, rendering the strain approach somewhat less attractive. The differences between the PM and VM cases indicate that threshold voltage adjustments by other means than doping profile modification (e.g. gate workfunction engineering) should be

References (36)

  • K. Rim et al.

    Strained Si CMOS (SS CMOS) technology: Opportunities and challenges

    Solid-State Electron.

    (2003)
  • C. Jungemann et al.

    Simulation of linear and nonlinear electron transport in homogeneous silicon inversion layers

    Solid-State Electron.

    (1993)
  • W. Hänsch et al.

    Carrier transport near the Si/SiO2 interface of a MOSFET

    Solid-State Electron.

    (1989)
  • S.S. Iyer et al.

    Heterojunction bipolar transistors using Si–Ge alloys

    IEEE Trans. Electron Devices

    (1989)
  • K. Ismail et al.

    High-transconductance n-type Si/SiGe modulation-doped field-effect transistors

    IEEE Electron Device Lett.

    (1992)
  • J. Welser et al.

    Strain dependence of the Performance Enhancement in Strained-Si n-MOSFETs

    IEDM Tech. Dig.

    (1994)
  • J.L. Hoyt et al.

    Strained silicon MOSFET technology

    IEDM Tech. Dig.

    (2002)
  • Rim K, Koester S, Hargrove M, Chu J, Mooney PM, Ott J, et al. Strained Si NMOSFETs for high performance CMOS...
  • S. Thompson et al.

    A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell

    IEDM Tech. Dig.

    (2002)
  • K. Ota et al.

    Novel locally strained channel technique for high performance 55 nm CMOS

    IEDM Tech. Dig.

    (2002)
  • T. Manku et al.

    Electron drift mobility model for devices based on unstrained and coherently strained Si1−xGex grown on 〈0 0 1〉 silicon substrate

    IEEE Trans. Electron Devices

    (1992)
  • M.V. Fischetti et al.

    Band structure, deformation potentials, and carrier mobility in strained Si, Ge and SiGe alloys

    J. Appl. Phys.

    (1996)
  • F. Bufler et al.

    Scaling of Strained-Si n-MOSFETs into the ballistic regime and associated anisotropic effects

    IEEE Trans. Electron Devices

    (2003)
  • Bude J, MOSFET modeling into the ballistic regime. In: Proc. SISPAD, 2000. p....
  • J.-S. Goo et al.

    Scalability of strained-Si nMOSFETs down to 25 nm gate length

    IEEE Electron Device Lett.

    (2003)
  • J.-S. Goo et al.

    Band offset induced threshold variation in strained-Si nMOSFETs

    IEEE Electron Device Lett.

    (2003)
  • K. Rim et al.

    Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs

    IEDM Tech. Dig.

    (2002)
  • C. Jacoboni et al.

    The Monte Carlo method for semiconductor device simulation

    (1989)
  • Cited by (0)

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