Investigation of strained Si/SiGe devices by MC simulation
Introduction
The SiGe technique has made bandgap engineering and mobility enhancement by strain available in the mainstream Si technology at a more competitive cost than in III–V technologies [1], [2]. Since the on-current of a MOSFET is strongly influenced by the effective low-field mobility in the inversion layer, strained Si layers with their higher mobility can be used to improve CMOS performance [3], [4]. Strained Si will be used in future CMOS generations [5], [6], where the strain can be induced not only by a relaxed SiGe layer in the bulk but also by gate processing [7]. In order to understand the transport properties and to explore the potential of this material, microscopic simulation models have been developed (e.g. [8], [9], [10]). The Monte Carlo (MC) model is especially well suited for this material system, because it contains only a few empirical parameters in contrast to less physics-based models (i.e. drift diffusion or hydrodynamic models), which require much more calibration. Consequently, due to the large degree of freedom in the SiGe alloy configuration (strain, Ge content, effects from new materials, etc) many more measurements are required for the calibration of the classical device models than for unstrained Si, and such measurements are still largely unavailable. Therefore, microscopic models like the MC model are preferable, although they are more CPU intensive. In addition, the momentum-based models become increasingly inaccurate under quasiballistic transport conditions and their results are unreliable in sub-50 nm devices [11].
It has been experimentally observed that the performance improvement due to strain decreases at smaller gate lengths [12]. In this paper we want to quantify the performance deterioration and explain the reasons for it.
The strain in the channel region of the MOSFET not only changes the mobility but also the threshold voltage, which decreases with strain [13], [14]. Therefore, in order to properly analyze the problem, we investigated three sets of devices: Unstrained Si control devices (CD), process matched (PM) strained Si NMOSFETs, which have same doping profiles as the control devices, and threshold voltage matched (VM) strained Si devices, where the doping profile is adjusted to match the threshold voltage of the control devices. The PM case allows to investigate the impact of strain on transport under almost the same electrical conditions as in the control devices, whereas the VM case is the more realistic one, which accounts for the degradation of the mobility due to the higher doping concentration required [15], [12].
Section snippets
Simulation model
The simulation model is based on the semi-classical Boltzmann equation neglecting degeneracy [16], where the band structure of strained Si is calculated with the nonlocal empirical pseudopotential method [17]. The details of the band structure are captured completely only by the full-band MC model, which is used here [18]. The corresponding scattering algorithms are so fast, that the full-band MC model is as efficient as an analytical-band simulator, where phonon, alloy, impurity, and surface
Strained Si NMOSFETs
In Fig. 1 the drift velocity in 〈1 1 0〉 direction is shown for different strain levels in an undoped bulk system consisting solely of strained Si. The low-field mobility is enhanced by strain, whereas the saturation velocity remains unaffected [23]. In addition, the low-field mobility enhancement saturates for high strain levels. Since the performance of a MOSFET is determined by the transport in the channel, MC simulations of inversion layers, which are homogeneous parallel to the Si/SiO2
Device simulation results
The three sets of devices described above have been simulated for a gate overdrive of 0.9 V, a lattice temperature of 300 K, and the 〈1 1 0〉 channel direction. Self-heating effects have not been considered. The relaxed SiGe layer in the bulk is neglected and the whole bulk is assumed to be strained Si to allow for an easier comparison between the strained and unstrained case. Simulations including the SiGe layer showed only negligible differences in the device performance.
In Fig. 5, Fig. 6 the
Conclusions
For the same doping profiles strained Si NMOSFETs yield a considerable on-current improvement even at a gate length of 23 nm. If the doping profile is modified to match the threshold voltage of the unstrained Si devices, the performance improvement degrades, rendering the strain approach somewhat less attractive. The differences between the PM and VM cases indicate that threshold voltage adjustments by other means than doping profile modification (e.g. gate workfunction engineering) should be
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