Elsevier

Applied Surface Science

Volume 453, 30 September 2018, Pages 31-36
Applied Surface Science

Full Length Article
Quantitative analysis of nano-defects in thin film encapsulation layer by Cu electrodeposition

https://doi.org/10.1016/j.apsusc.2018.05.072Get rights and content

Highlights

  • Quantitative analysis of the pinholes in SiON thin film encapsulation is provided.

  • Kinetic growth rate of electrodeposited Cu bumps on the pinholes was established.

  • Pinhole size was deduced from the kinetic growth curve of the Cu bumps.

  • Dissolved Ni underlayer involved in the formation of the Cu bumps.

Abstract

Thin-film encapsulation (TFE) is of great importance as a barrier film to protect organic devices and displays. A serious problem with the application of TFE is degradation of organic devices with penetration of oxygen and water vapor through pinholes having sub-micron size. Though many studies were tried to identify the pinholes, quantitative analysis of pinhole area has not been found yet. In this study, total pinhole area in TFE layer was quantitatively analyzed with the help of the Cu bumps electrodeposited on the pinholes. Empirical growth rate of the Cu bumps revealed that bump radius (r) and plating time (t) had a relationship of r3 ∝ t. While size of the pinholes was deduced from starting point of Cu bump growth, number of the pinholes was extracted from size distribution of the Cu bumps. Unique feature of Cu bump morphology is also explained with a compositional analysis, demonstrating dissolution of Ni underlayer and its involvement in the formation of the Cu bumps.

Introduction

Organic electronics have been intensively developed for various applications in recent years. Organic photovoltaic cells and thin-film light emitting diodes (LED) have been demonstrated [1], [2]. Transistors based on organic semiconductors have drawn significant interest from researchers in the field [3]. However, the efficiency of organic devices such as LEDs, solar cells, and transistors is still inferior to that of silicon-based inorganic electronic devices. One of the important reasons for this is the instability of organic materials while operating in ambient conditions, which reduces the long-term reliability. Therefore, to achieve reliable performance in organic devices, many technologies have been used to encapsulate the organic parts in the electronic devices. A well-known Barix technology, deposition of alternative dyads of organic and inorganic films as barrier layers, efficiently protects the devices from corrosion due to water vapor and oxygen permeation [4]. Direct coverage by thin-film encapsulation (TFE) was also successfully demonstrated using Vitex multilayer technology with the implementation of three or less dyads [5]. The technology with varying TFE deposition is currently used for development and production and is expected to be applied for the next generation of flexible displays and devices. However, up to now, no commercial product has been introduced in the market using TFE technology, since it is still expensive because of high investment and low throughput.

At first, encapsulation of organic devices was achieved with rigid materials such as glass and metal lids [6]. However, these materials could not be used for typical flexible devices. Therefore, approaches for flexible encapsulation have been developed: ultra-thin glass, barrier-coated flexible lids, vacuum deposited thin films and so on [7], [8], [9]. Various deposition methods, such as thermal evaporation, sputtering, chemical vapor deposition (CVD) and atomic layer deposition (ALD) have been used for TFE application. Among these, CVD and ALD are most frequently used these days [10], [11], [12], [13]. A serious problem with TFE is degradation of organic devices that occurs due to penetration of oxygen and water vapor through pinholes generated during deposition process. Formation of the pinholes is known to be caused by the presence of dust particles on the polymer surface during TFE deposition [14], [15]. Dust particles block the deposition and leave unmetallized shadows. In addition, scuffing of the particles on the surface could also function as a source of pinhole defects [14]. Precise observation and analysis of morphology and density of the pinholes are important as a first step to figure out prevention methods against pinhole formation. Clear identification of the pinholes is not easy since their size is usually in the range of several nanometers to several tens of nanometers. Zhang et al. visualized the pinholes using fluorescent tags that could identify cracks having a width of ∼20 nm under applied strain and individual defects as small as ∼200 nm in diameter [16]. Singh et al. reported that O3 pulse duration had a strong influence on the diffusion barrier properties, which were evaluated using X-ray reflectometry (XRR) [17]. Meanwhile, electroplating of Cu bumps on the pinholes was reported as an easy way of visualization that could be realized using conventional microscopy [18]. Several researchers used this method to quantify the number of pinholes formed in TFE layers where size of the Cu bumps was generally much larger than that of the pinholes [19], [20]. Though the Cu bump method was helpful to count number of the pinholes, pinhole area has not been clarified yet. In this study, quantitative analysis of pinhole area, including both number and size of the pinholes, is introduced by the help of the Cu bumps electrodeposited. Growth rate of the Cu bump was identified by comparing theoretical calculation with experimental data. Pinhole diameter was deduced from a universal curve of Cu bump growth, while pinhole number was extracted from size distribution of the Cu bumps. Unique feature of Cu bump morphology will also be explained with close observation and compositional analysis for root of the Cu bump.

Section snippets

Experimental

In this study, a SiON barrier film was employed for TFE application. First, a conductive seed layer (100 nm-thick Ni on 50 nm-thick Ti) was deposited by e-beam evaporation on an 8-inch silicon wafer. Then, the SiON films were deposited by plasma enhanced chemical vapor deposition (PECVD) on the seed layer. Precursors used for PECVD were SiH4, N2, and NH3 for SiNx and SiH4, N2O, and NH3 for SiOx deposition, respectively. The precursors were fed into a vacuum chamber at user-defined mass flow

Microstructural and compositional analyses of the Cu bumps

A schematic of an electroplated Cu bump is presented in Fig. 1(a). During the PECVD process of SiON TFE layer, some pinholes formed in the SiON films. Size (diameter) of the pinholes ranged from several nanometers to several hundreds of nanometers, and only small portion of them has the size over 1 µm. The literature [21] reported that formation of the pinholes is closely related with surface contamination of the substrate on which the TFE layers are deposited. Therefore, pinhole density

Conclusions

In this study, quantitative analysis of the pinholes which formed in SiON thin film encapsulation layer is introduced with the aid of electrodeposited Cu bumps. Total pinhole area was estimated using number of the Cu bumps and pinhole size determined from the curve of Cu bump growth. Theoretical relationship between bump radius and plating time, r3 ∝ t, was verified using the Cu bumps electrodeposited on the artificial pinholes fabricated with photolithography process. Pinhole size was deduced

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