Elsevier

Solid-State Electronics

Volume 141, March 2018, Pages 65-68
Solid-State Electronics

Enhanced transconductance in a double-gate graphene field-effect transistor

https://doi.org/10.1016/j.sse.2017.12.008Get rights and content

Highlights

  • A double-gate structure is adopted for a graphene transistor.

  • Maximum transconductance is enhanced 50% by using the double-gate structure.

  • Using a compact model, the enhanced transconductance is quantitatively explained.

Abstract

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Introduction

Graphene has attracted considerable interest as a promising material for high-performance electronic devices due to its unique physical properties, such as atomically thin thickness [1], flexibility [2], high carrier mobility [3], [4], and high thermal conductivity [5]. Due to the zero bandgap of graphene, the possible applications of graphene field-effect transistors (GFETs) are considered to be more suitable for high-frequency analog electronics [6], [7], [8], or detectors [9], [10], rather than digital logic technology which requires a definite switching capability between an “on” and “off” state. One of the fundamental performance metrics of a FET is the controllability of the gate over the channel resistivity which is manifested as the transfer characteristics.

The transfer characteristics of GFETs have been extensively studied with a variety of structural considerations including a hexagonal boron nitride (hBN) substrate [11], a solution gate [12], a side gate [13], a high-quality gate dielectric layer [14] and a folded graphene channel [15]. Although it has been well-known in CMOS technology that a multi-gate structure, the mainstream of state-of-the-art nanoscale transistor design nowadays, greatly improves gate-to-channel control efficiency of a transistor [16], [17], few studies have been done on the application of the multi-gate technique to GFETs. This raises the question of whether the advantage of a multi-gate structure that has been developed for several-nanometer-thick Silicon channel can still be effective for the one-atom-thick 2D channel. Furthermore, the previously reported double-gate structure of graphene transistors refers only to a metallic top gate and silicon substrate gate that act as two independent electrodes [18], [19], [20], [21], [22], not a pair of connected electrodes that applies an electric field symmetrically and simultaneously to both sides of the graphene channel. It should be noted that the aforementioned GFET is not a genuine double-gate structure but a quasi double-gate structure.

In this work, we report the fabrication of a double-gate graphene field-effect transistor (DG GFET) that is capable of modulating the graphene channel by the top and bottom gate simultaneously and symmetrically. The transfer characteristics of the fabricated DG GFET were compared to those of the single-gate graphene field-effect transistor (SG GFET) counterpart. The different characteristics between the SG and DG GFETs were further examined with a compact model for GFETs.

Section snippets

Experimental details

A highly doped (1–3 mΩ⋅cm) silicon wafer with a 90-nm-thick thermal SiO2 was used as a substrate for the device fabrication. The bottom gate for the DG structure was patterned on a SiO2 substrate with photolithography, and a Cr/Au (3/40 nm) stack was deposited with thermal evaporation. The bottom-gate dielectric film consists of a high-κ dielectric of 20-nm-thick Al2O3 film deposited by atomic layer deposition (ALD). Subsequently, a CVD-grown monolayer graphene was transferred onto the Al2O3

Results and discussion

Fig. 1(a) shows a cross-sectional schematic of the DG GFET developed in this work. The graphene channel is encapsulated by the Al2O3 dielectric layers at the top and bottom interface. The cross-sectional transmission electron microscopy (TEM) images of the DG GFET in Fig. 1(b) confirms that the double-gated structure and dielectric layers of Al2O3 were successfully fabricated as designed. The device used in this study had a gate length of 4 μm and a channel width of 6.5 μm. The gate underlap,

Conclusion

We have fabricated DG GFETs and investigated their transfer characteristics in comparison with SG GFETs. The maximum transconductance of the GFET showed a 50% improvement by introducing an additional gate (double-gate). This improvement was also reproduced with an analytical model for GFETs, and the contribution of carrier density and velocity was calculated. This study showed experimentally that the application of a double-gate structure to a graphene transistor has an advantage in terms of

Acknowledgement

This research was supported by the Pioneer Research Center Program through the National Research Foundation of Korea, which is funded by the Ministry of Science, ICT & Future Planning (Grant No. 2012-0009600). This work was also supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2011-0031848).

Yang-Kyu Choi received the B.S. and M.S. degrees from Seoul National University, Seoul, South Korea, in 1989 and 1991, respectively, and the Ph.D. degree from the University of California at Berkeley, Berkeley, CA, USA, in 2001. He is currently a professor with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea.

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    Yang-Kyu Choi received the B.S. and M.S. degrees from Seoul National University, Seoul, South Korea, in 1989 and 1991, respectively, and the Ph.D. degree from the University of California at Berkeley, Berkeley, CA, USA, in 2001. He is currently a professor with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea.

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