Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination
Introduction
Transparent metal oxide semiconductors such as amorphous indium gallium zinc oxide (a-IGZO) as channel materials for thin film transistors (TFTs) have high electron mobility, excellent uniformity, low-temperature fabrication process, and good transparency; they are therefore promising for use in next-generation displays [1]. We evaluate a-IGZO TFTs as the backplane technology for next-generation active matrix liquid crystal displays and organic light-emitting diode displays [1], [2]. Despite their promising features, a-IGZO TFTs are unreliable when subject to factors such as ambient gases, temperature, moisture, gate voltage VGS bias, drain voltage VDS bias and illumination [3], [4], [5], [6], [7].
In real application, a-IGZO TFTs are driven in turn-on state (VGS and VDS > 0) and turn-off state (VGS = 0 and VDS > 0) for a long time under illumination. VDS is applied to TFTs for both states, so the effect of long-term drain bias under illumination should be clarified to assure stability in practical operation. Instability of a-IGZO TFTs under drain bias illumination temperature stress (DBITS), i.e., turn-off state under illumination, have been studied [8], [9]. Defect creation [8] and hole trapping on the interface between active layer and gate insulator GI or in the GI [9] are accepted mechanism to explain negative shift of I-V characteristics, but the mechanism by which a-IGZO TFTs degrades under long-term DBITS has not been investigated.
In this work, we investigated the mechanism of degradation behavior under long-term (200,000 s) DBITS. After DBITS, the I-V characteristics of a-IGZO TFTs shift negatively with a degradation of subthreshold slope SS for stress time tS = 10,000 s, but extended tS > 40,000 s induces a hump phenomenon in the subthreshold region of the I-V curve; as a result the transistor turns on early. We used capacitance–voltage C-V measurement and a two-dimensional device simulation to clarify that this hump phenomenon in the I-V curves is caused by creation of shallow donor-like states, i.e., ionized oxygen vacancies VO2+, near the drain side of TFT and migration of VO2+ from the drain side to the source side of TFT.
Section snippets
Experimental methods
We fabricated a-IGZO TFTs on glass substrate with bottom-gate, back-channel-etch structure [10]. Mo-Ti was used as the electrodes and SiO2 was used as gate insulator and passivation layer. (Fig. 1). The I-V characteristics of a-IGZO TFTs were analyzed using an Agilent 4156A semiconductor parameter analyzer. To apply DBITS, VGS = 0 V was applied to the gate electrode and VDS = 40 V was applied to the drain electrode while the source electrode was grounded under white light illumination
Results and discussion
DBITS induced two-stage degradation in the I-V characteristics of the a-IGZO TFTs (Fig. 2a). During the early stage of stress, I-V characteristics of the TFTs shifted negatively with SS degradation for tS < 10,000 s (ΔSS = +187 mV/dec from initial state to 10,000-s state) (Fig. 2b); this degradation indicates that defect creation is the main cause of the degradation [11], and also hole trapping could occur on the interface between active layer and GI or in the GI [3]. The hump phenomenon in I-V
Conclusions
We investigated the degradation mechanism of back-channel-etched a-IGZO TFTs under DBITS. Two-step degradation was observed during long-term DBITS. During the early stages of stress, the I-V characteristics shift negatively with SS degradation. Extended DBITS induced the hump phenomenon in I-V characteristics. We qualitatively confirmed the relationship between the hump phenomenon and the peak density of shallow donor-like states (i.e., oxygen vacancies VO2+). Stretched-out CGD-VG and the
Acknowledgments
This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, Under the “ICT Consilience Creative Program” (IITP-R0346-16-1007) supervised by the IITP (Institute for Information & communications Technology Promotion). This work also was supported by LG Display. The author thanks LG Display for the technical support.
Yong-Jung Cho received the B.S. degree in electrical engineering from Kyungpook National University, Daegu, Korea, in 2014, and is currently pursuing the Ph.D. degree in the Department of Electrical Engineering in Pohang University of Science and Technology (POSTECH). His research interest is amorphous oxide thin-film transistors for application in display devices.
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Yong-Jung Cho received the B.S. degree in electrical engineering from Kyungpook National University, Daegu, Korea, in 2014, and is currently pursuing the Ph.D. degree in the Department of Electrical Engineering in Pohang University of Science and Technology (POSTECH). His research interest is amorphous oxide thin-film transistors for application in display devices.
Ohyun Kim received the B.S. degree in electrical engineering from Seoul national University, in 1977, and the M.S. and Ph.D. degrees from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1983. From 1983 to 1986, he was with Samsung Electronics, Korea, where he was involved in DRAM development. From 1989 to 1990, he was with Bell Communications Research, NJ, USA; during the period his research was focused on high speed devices. Since 1986, he has been a Professor in the Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH). His research interests include EUV lithography, polymer memories, AMOLEDs, Oxide TFTs, Graphene FETs and ReRAMs, and strained high-voltage MOSFETs.