Channel scaling and field-effect mobility extraction in amorphous InZnO thin film transistors
Introduction
Amorphous oxide semiconductors (AOSs) based on In2O3 are technologically promising due to high carrier mobility [1], [2], [3] and excellent optical transmittance [1] in the visible. Therefore, AOS materials have been integrated as active layers [2], [4] and electrodes [2], [5], [6] into a variety of electronic devices, such as high performance thin film transistors [2], [7] (TFTs) and fast photodetectors [8], [9]. This class of materials has been gaining particular attention in next generation displays due to their much higher TFT field effect mobility μFE (>10 cm2/V·s vs. 1 cm2/V·s) [1], [2], [3] and low temperature (T) processability (RT–100 °C vs. ∼300 °C) [1], [2], [3], [4] compared to conventional amorphous Si (a-Si)-based TFTs. Additional advantages of AOSs include isotropic wet etch characteristics [7] and compatibility with mass production [10], all of which make this material suitable for large area, flexible, and transparent devices on inexpensive polymer substrates [11].
To date, many researchers have extensively contributed to the development of high-performance and stable AOS TFTs. These efforts include studies of thermal [12] and bias stress [13], [14] stability, the elucidation of doping mechanisms [15], [16], threshold voltage stability [12], [13], [14], [17], the investigation/improvement of channel/metallization contact properties [2], [18], [19], and amorphous phase stability [12], [20]. Therefore, some AOS materials such as InGaZnO (IGZO) are now being deployed in high performance and flexible active-matrix liquid crystal displays and active-matrix organic light emitting diode technologies [10]. Compared to industrialized IGZO TFTs, IZO TFTs have shown markedly higher field-effect mobility [4], [12], making them promising for high-current devices in future technologies.
An important future technological challenge is the downscaling of AOS TFTs for ultra-high definition (UHD) displays. Since these next-generation technologies utilize much smaller pixel sizes for UHD resolution, AOS TFTs employed as pixel driving elements must be scaled down as well. When the dimensions of TFT devices (e.g., channel length L and width W) are reduced, important device characteristics such as the field-effect mobility μFE, threshold voltage VT, and device saturation behavior are expected to be affected by scaling, like conventional metal-oxidesemiconductor field effect transistor (MOSFET) devices. Previous studies by Jeong et al. [21] and Barquinha et al. [22] reported that the field-effect mobility of sputter-processed amorphous IGZO TFTs decreased from ∼10 cm2/V·s to 3.5 cm2/V·s (IZO source/drain or S/D) and ∼24 cm2/V·s to 10 cm2/V·s (IZO, Ti/Mo S/D) as channel length L was downscaled. They attributed these μFE decreases to the effect of increasing parasitic resistance. Hu et al. [23] found a similar behavior in solution-processed ZnSnO TFTs, where μFE decreased from 8 to 6 cm2/V·s (Mo S/D) and from 6 to 1 cm2/V·s (Ti/Au S/D) as L was scaled down from 300 μm to 3 μm, again attributing the decrease in μFE to contact resistance. In the reports by Jeong [21] and Barquinha [22], the difference between Mo and Ti/Au metallized devices was attributed to the formation of TiO2 in the Ti/Au S/D case. These reports are in basic agreement with our previous study [12] that suggested metallization strategies for AOS-based TFTs to ensure low contact resistance. However, while the previous reports [21], [22], [23] described the channel scaling-induced μFE reduction, a method to correctly evaluate μFE in downscaled AOS-based TFTs was not provided.
In this study, we report on the effect of channel downscaling in amorphous InZnO (a-IZO) TFTs on the device performance. Backgated devices with various L and W were fabricated, and the output and transfer characteristics were compared as a function of L. We have found that the extracted µFE decreases strongly with L: from 39.3 cm2/V·s (L = 50 µm) to 9.9 cm2/V·s (L = 5 µm), while the threshold voltage VT became more negative in small L devices and, furthermore, smaller devices required a larger drain bias VD to achieve drain current saturation and show higher off-state currents. Transmission line model (TLM) measurements and a modified extraction procedure were used to evaluate the effect of contact resistance at the channel/metallization interface and its subsequent impact on the extraction of µFE in a-IZO TFTs with channel scaling.
Section snippets
Experimental details
In our a-IZO TFTs, the channel, source/drain (S/D), and gate contact electrodes were deposited at room temperature using dc magnetron sputtering with a target-to-substrate distance of 10 cm. Before all depositions, the sputter chamber was pumped down to a base pressure lower than 6 × 10−6 Torr and the target was pre-sputtered for 1000 s to remove surface contamination and to ensure homogeneous distribution of process gas in the sputter chamber. To investigate the channel IZO and the channel scaling
Results and discussion
The drain current–voltage (ID-VD) output characteristics were measured by sweeping VD from 0 to 15 V at fixed VG that ranged in 2 V steps from −10 to 10 V. An inset in Fig. 1(a) shows a top view schematic (not to scale) of IZO TFTs used in the present study, where the Mo S/D electrode length is 100 μm. Fig. 1(a–d) presents the typical ID-VD plots of the a-IZO TFTs with W/L = 100/50, 100/20, 100/10 and 100/5 μm, respectively, showing the significant effect of the channel downscaling on the output
Conclusion
In conclusion, as the channel length L of IZO TFTs is scaled down, direct experimental extraction of the field-effect mobility severely underestimates it due to increasing series contact resistance effects. The increasing RC/RTotal ratio leads to a decrease in effective VD and VG. The TLM measurements and theoretical analysis provide the corrected ID-VD curves, from which the corrected field-effect mobility can be extracted. In our backgated IZO TFTs, this corrected field effect mobility is as
Acknowledgments
This work was supported by the Baylor University faculty start-up funds. The Brown-based co-authors (YS, AZ, and DCP) acknowledge the financial support of the National Science Foundation, NSF award DMR-1409590.
Sunghwan Lee received the Ph.D. degree from Brown University in 2013. He was a post-doctoral scientist at MIT and Harvard University from 2013 to 2015. He joined Baylor University in the Fall, 2015, where he is currently an Assistant Professor of Mechanical Engineering and Materials Science. His research interests are focused on transparent and flexible electronics, thin film transistors and energy conversion devices.
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Cited by (0)
Sunghwan Lee received the Ph.D. degree from Brown University in 2013. He was a post-doctoral scientist at MIT and Harvard University from 2013 to 2015. He joined Baylor University in the Fall, 2015, where he is currently an Assistant Professor of Mechanical Engineering and Materials Science. His research interests are focused on transparent and flexible electronics, thin film transistors and energy conversion devices.
Yang Song received his ScB in physics from Nanjing University, 2012. He is currently pursuing his PhD at Brown University. His research interests are focused on amorphous oxide semiconductors, thin film transistors and semiconductor devices.
Hongsik Park received the Ph.D. degree from Brown University in 2011. He was a researcher at Samsung Advanced Institute of Technology, Korea from 1999 to 2006. He also worked at IBM T. J. Watson Research Center as a research staff member from 2011 to 2014. He is currently an associate professor at the School of Electronics Engineering at Kyungpook National University, Korea. His research interests are focused on integration of nanomaterial-based devices with conventional Si devices for Si photonics and integrated sensor applications.
Alexander Zaslavsky received the Ph.D. degree from Princeton University in 1991. He was a post-doctoral scientist with IBM T. J. Watson Research Center from 1991 to 1993. He joined Brown University in 1994, where he is currently a Professor of Engineering and Physics. He has also been a visiting Senior Chair at the Grenoble Polytechnic Institute 2009-12. His research interests are focused on semiconductor device and nanostructure physics, particularly tunneling and hot-electron devices.
David C. Paine received the Ph.D. degree from Stanford University in 1988. He joined Brown University in 1989, where he is a Professor of Engineering in the Materials Science group. His research interests are currently focused on transparent conducting oxides, amorphous oxide semiconductors, electron microscopy and thin film deposition and processing.