LetterInstability investigation of In0.7Ga0.3As quantum-well MOSFETs with Al2O3 and Al2O3/HfO2
Introduction
Indium-rich InxGa1−xAs channel materials, x > 0.53, have re-gained their interest, and now stand out as the most promising non-Si n-channel material for next-generation low-power and high-performance logic applications at 5-nm technology-node and/or beyond [1], [2], [3]. This is a consequence of their superior electron carrier transport properties, such as electron mobility (μn,Hall) in excess of 10,000 cm2/V-sec and electron injection velocity (vinj) over 3 × 107 cm/s at room temperature [4], [5]. To maximize benefits of using III–V channel materials with high electron mobility, it is of critical importance to minimize all the traps, associated with high-k dielectric layers adjacent to III–V channel materials. In fact, those traps deteriorate a subthreshold-swing (S) and mobility in the channel and therefore degrade an ION/IOFF ratio4. To date, there are only a few reports on relevant reliability issues in InGaAs MOSFETs [6], [7]. A charge-trapping mechanism in the high-k dielectric materials during device operation can cause a frequency dispersion and shift in VT (ΔVT), causing a severe reliability concern [6], [7].
In our previous works, we reported on In0.7Ga0.3As quantum-well (QW) MOSFETs with equivalent-oxide-thickness (EOT) of less than 1 nm, using a bi-layer Al2O3/HfO2 gate stack [8]. In this paper, we carry out a comprehensive reliability study on InGaAs MOSFETs with single-layer Al2O3 and bi-layer Al2O3/HfO2 III–V gate stacks, in an effort to identify the impact of traps in different high-k dielectric layers. In addition, we perform a cryogenic DC measurement for In0.7Ga0.3As QW MOSFETs to try to freeze out traps at the interface (Dit) between In0.7Ga0.3As channel and high-k dielectric layer. Clearly, we observe that the device with bi-layer Al2O3/HfO2 gate stack induces more charge-trapping phenomena than one with Al2O3 gate stack.
Section snippets
Process technology
Fig. 1(a) and (b) shows a cross-sectional cartoon of an In0.7Ga0.3As quantum-well (QW) MOSFET with high-k gate stacks and an energy-band diagram for InGaAs gate stack with bi-layer dielectric scheme, highlighting the interaction of channel carriers with interface traps and oxide traps, so called “border traps”. After high-k gate stack deposition to an In0.7Ga0.3As channel, a TiN metal-gate (MG) with 5 nm was deposited in an in-situ manner by ALD. Generally, the interface control layer (ICL)
Results and discussion
Fig. 2(a) and (b) shows capacitance–voltage (C–V) characteristics from long-channel (Lg = 10 μm) In0.7Ga0.3As QW MOSFETs with frequency sweeping from 10 kHz to 1 MHz. High-resolution TEM images for both gate stacks are shown in the inset of Fig. 2(a) and (b). Note that both devices exhibit fairly small values of the frequency dispersion behavior in the accumulation region. In particular, the device with Al2O3 exhibit the frequency dispersion of 5.24%, and one with Al2O3/HfO2 the frequency dispersion
Conclusion
In conclusion, we have carried out a comprehensive reliability study on InGaAs QW MOSFETs. Although planar Lg = 5 μm InGaAs QW MOSFET with Al2O3/HfO2 have shown excellent electrostatics, such as SS = 69 mV/dec. and DIBL < 10 mV/V, however, we have observed that the bi-layer Al2O3/HfO2 gate stack yields more charge trapping phenomenon, causing more ΔVT under CVS and hysteresis behavior at cryogenic temperature. These, in turn, deteriorate the reliability characteristics, as opposed to the device with
Acknowledgements
This work was supported by both grants from the R&D Program funded by the Ministry of Science, ICT and Future Planning (MSIP), (Grant No. NRF-2014M3A7B5073451) and the BK21 Plus program at Kyungpook National University funded by the Ministry of Education (21A20131600011).
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Cited by (1)
Border traps and bias-temperature instabilities in MOS devices
2018, Microelectronics ReliabilityCitation Excerpt :That such annealing treatment can lead to a significant reduction in border-trap density is confirmed in C-V measurements in that study, and in others, e.g., Fig. 15, in which as-deposited films show a much larger C-V hump than do H2-annealed films [33]. These border traps lead to significant bias instabilities in InxGa1-xAs-based MOSFETs, even at modest biases and at room temperature [85–88], owing to the relatively high densities of border traps and their accessible energy levels [32,89,90]. They also contributed to radiation-induced charge trapping, as illustrated by current-voltage and capacitance-frequency measurements in Fig. 16 [91].
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Hyuk-Min Kwon and Do-Kywn Kim contributed to this work equally.