Low-temperature electrical characterization of junctionless transistors
Highlights
► Junctionless transistors (JLTs) with planar structures were fabricated on SOI wafers. ► JLT μ0 is limited by phonon and neutral defect scattering for long lengths. ► JLT μ0 is limited by Coulomb and neutral defect scattering for short lengths. ► The temperature dependence of Vfb and Vth is similar in JLT devices. ► The less short channel effect in subthreshold swing is a strong advantage of JLT.
Introduction
Junctionless transistors (JLTs) are currently in the spotlight, owing to the advantages which are expected from their simple structure, without PN junctions, and from their operation principle, based on bulk conduction instead of surface conduction for the standard inversion-mode (IM) MOSFET [1]. For example, JLT devices are known as more robust than IM transistors in terms of effective gate length variability and mobility degradation by transverse electric field. However, JLT devices are facing some issues such as mobility degradation by their high channel doping, reduced gate controllability due to partial depletion regions, and threshold voltage variability induced by fluctuation of silicon thickness and doping atoms spatial distribution. Many specific electrical properties of JLT devices have been investigated, so far mainly at room temperature [1], [2], [3], [4]. In particular, JLT devices with planar structures recently revealed very interesting features, including two peaks in the plots of transconductance derivative, which distinguish the (bulk) neutral and (surface) accumulation channels [5]. Only few papers have dealt with low temperature operation, concentrating mainly on the identification of conductance oscillations in nanowire JLTs [6], and on temperature dependence of the threshold voltage of such narrow structures [7]. More generally, low-temperature characterization allows for a better understanding of physical operation and electrical performance of electronic devices [8], [9]. Extraction of the electrical parameters of JLT devices in the low-temperature range is a powerful tool to get deeper insight into their operation mechanism and more quantitative information about their performance.
This paper deals with JLT devices with a planar structure (W = 10 μm) fabricated from silicon on insulator (SOI) wafers with a silicon thickness tsi of 9.4 nm. The electrical parameters of JLT devices were extracted at low-temperature and compared to those of IM transistors fabricated by the same process including an additional implantation on source and drain (S/D) regions, except for channel doping concentration. The electrical performances of JLT devices, including scattering mechanisms and short channel effects, are discussed based on an analysis of temperature dependence of low-field mobility, threshold voltage, flat-band voltage and subthreshold swing.
Section snippets
Device fabrication and experiment
This study was based on N-type JLT devices with high-κ/metal gate stack, fabricated at CEA-LETI on (100) SOI wafers with 145 nm thick buried oxide (BOX) and a Si body thinned down to 9.4 nm. A full-sheet implantation was performed before active patterning with a phosphorus doping targeted at 1 × 1019 cm−3 or 2 × 1019 cm−3. The gate is composed of HfSiON/TiN/Polysilicon, with an equivalent oxide thickness of 1.2 nm. An additional implantation was performed to S/D regions with the aim of improving
I–V characteristics at low-temperature
Drain current (Id) of JLT devices for short and long gate lengths (i.e. effective length Leff = 20 nm, and L = 1 μm, respectively) was measured as a function of gate voltage (Vg), with temperature varying in the range of 80–350 K (Fig. 2a and c). The common intersection point, the so called zero-temperature coefficient (ZTC) point [11], where Id does not depend on temperature due to the compensated temperature effects of mobility and conduction threshold voltage (Vth), was found only for long gate
Conclusions
Junctionless transistors (JLT) with planar structures (W = 10 μm) were fabricated on (100) SOI wafers with 145 nm thick BOX and 9.4 nm thick silicon. The electrical performances of the JLT devices were investigated under low temperature, in the range of 80–350 K, and compared to those of inversion-mode (IM) transistors featuring the same structure, and fabricated by the same process except for channel doping level. From its overall temperature dependence, it was found that the low-field mobility (μ0)
Acknowledgements
This work was supported by European Union 7th Framework Program project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Converging Research Center Program, 2012K001313 and Global Frontier Research Program, No. 2011-0031638). The authors also thank Xavier Mescot and Martine Gri for their help in operating the cryogenic probe station system.
References (19)
- et al.
Brief review of the MOS device physics for low temperature electronics
Solid State Electron
(1994) - et al.
A review of some charge transport properties of silicon
Solid State Electron
(1977) - et al.
Nanowire transistors without junctions
Nat Nanotechnol
(2010) Electronic devices: nanowire transistors made easy
Nat Nanotechnol
(2010)- et al.
Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm
Electron Device Lett IEEE
(2011) - et al.
Reduced electric field in junctionless transistors
Appl Phys Lett
(2010) - Jeon D-Y, Park SJ, Mouis M, Berthome M, Barraud S, Kim G-T, Ghibaudo G. Electrical characterization and revisited...
- et al.
Low-temperature conductance oscillations in junctionless nanowire transistors
Appl Phys Lett
(2010) - et al.
Cryogenic operation of junctionless nanowire transistors
IEEE Electron Device Lett
(2011)
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